Hardware overview: Difference between revisions
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*'''CPU''': Hitachi SuperH SH-4 RISC CPU @ 200MHz | *'''CPU''': Hitachi SuperH SH7750 SH-4 RISC CPU @ 200MHz | ||
**200 MHz/360 MIPS at 3.3V I/O, 1.8V internal | |||
**16 x 32-bit general purpose registers | |||
**32 x 32-bit single-precision floating point registers | |||
**16-bit fixed instruction length for high code density | |||
**5 stage pipeline | |||
**On-chip cache, 8KB instruction and 16KB data | |||
*'''GPU''': NEC PowerVR2 with 8MB of [[VRAM|texture memory]] | *'''GPU''': NEC PowerVR2 with 8MB of [[VRAM|texture memory]] | ||
*'''Sound''': Yamaha AICA (64 channel PCM sound) with 2MB memory | *'''Sound''': ARM7DI-based Yamaha AICA (64 channel PCM sound) with 2MB memory | ||
*'''Memory''': 16MB system memory | *'''Memory''': 16MB system memory | ||
*'''Storage''': [[GD-ROM drive]] | *'''Storage''': [[GD-ROM drive]] | ||
*'''Network''': 33.6K or 56K [[Modem|modem]] | *'''Network''': 33.6K or 56K [[Modem|modem]] | ||
[[:File:150-000105-1e SegaDreamcast.pdf|Sega Dreamcast Electronic Game Performance and Design Analysis by Portelligent]] | |||
Latest revision as of 23:24, 19 April 2023
- CPU: Hitachi SuperH SH7750 SH-4 RISC CPU @ 200MHz
- 200 MHz/360 MIPS at 3.3V I/O, 1.8V internal
- 16 x 32-bit general purpose registers
- 32 x 32-bit single-precision floating point registers
- 16-bit fixed instruction length for high code density
- 5 stage pipeline
- On-chip cache, 8KB instruction and 16KB data
- GPU: NEC PowerVR2 with 8MB of texture memory
- Sound: ARM7DI-based Yamaha AICA (64 channel PCM sound) with 2MB memory
- Memory: 16MB system memory
- Storage: GD-ROM drive
- Network: 33.6K or 56K modem
Sega Dreamcast Electronic Game Performance and Design Analysis by Portelligent