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|0x00000000-0x7FFFFFFF (Physical address space repeats 4 times) | |0x00000000-0x7FFFFFFF<br />(Physical address space repeats 4 times) | ||
|Address translation through MMU (if enabled) | |Privileged mode or user mode.<br />Address translation through MMU (if enabled). | ||
|U0/P0 | |U0/P0 | ||
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|0x0C000000-0x0FFFFFFF | |0x0C000000-0x0FFFFFFF | ||
Latest revision as of 18:08, 13 January 2023
Introduction
The Dreamcast uses 32-bit logical addresses, but the physical address range is only 29-bit. [1] When the built-in MMU is active, the mapping between logical and physical address is basically left up to the programmer (see the SH4 Hardware Manual for details), however the normal mode of operation in the Dreamcast is to have the MMU disabled, in which the mapping is fixed as described below.
Logical address format
When the MMU is disabled, the 32-bit logical addresses have the following format:
| 31 | 30 | 29 | 28 ... 0 |
|---|---|---|---|
| P | ALT | NC | Physical address |
Modifier Bits
In addition to the physical address, the following modifier bits are used:
| P | Privileged Access | Addresses with the P bit set can only be accessed when the CPU is running in privileged mode, that is when the MD bit in the status register is set.
An exception to this is the Store Queue though. P inhibits the MMU, and enables the ALT and NC bits. If P is not set, ALT and NC are ignored. |
|---|---|---|
| ALT | Alternate Address Space | Setting this bit gives an alternate mapping of the physical address bits.
If NC is also set, the builtin CPU I/O registers are selected. If NC is not set, MMU translation is selected (if MMU is enabled) even though P is set. |
| NC | Not Cacheable | Setting this bit circumvents the data cache, which is useful for accessing external hardware registers. |
Modifier Bit Combinations
The following table shows the possible combinations of the modifier bits:
| P | ALT | NC | Address range | Description | Area name |
|---|---|---|---|---|---|
| 0 | X | X | 0x00000000-0x7FFFFFFF (Physical address space repeats 4 times) |
Privileged mode or user mode. Address translation through MMU (if enabled). |
U0/P0 |
| 1 | 0 | 0 | 0x80000000-0x9FFFFFFF | Privileged mode only. | P1 |
| 1 | 0 | 1 | 0xA0000000-0xBFFFFFFF | Privileged mode only, no cache. | P2 |
| 1 | 1 | 0 | 0xC0000000-0xDFFFFFFF | Privileged mode only. Address translation through MMU (if enabled). | P3 |
| 1 | 1 | 1 | 0xE0000000-0xFFFFFFFF | Privileged mode only. Internal I/O register access. No cache. | P4 |
Physical address format
With exception of the P4 area, the different logical address areas share the same physical address space. This address space (of 29 bits) is divided into eight different areas of 64MB size each.
| Physical address | Contents | Name |
|---|---|---|
| 0x00000000-0x03FFFFFF | Boot ROM (2MB)
Flash ROM (256K) Hardware registers |
Area 0 |
| 0x04000000-0x07FFFFFF | Video RAM (8MB) | Area 1 |
| 0x08000000-0x0BFFFFFF | Area 2 | |
| 0x0C000000-0x0FFFFFFF | System RAM (16MB) | Area 3 |
| 0x10000000-0x13FFFFFF | Tile accelerator command input | Area 4 |
| 0x14000000-0x17FFFFFF | Expansion (modem) port | Area 5 |
| 0x18000000-0x1BFFFFFF | Area 6 | |
| 0x1C000000-0x1FFFFFFF | Internal I/O registers (same as P4) | Area 7 |
Accesses to Area 7 require the CPU to be running in privileged mode even if the access is through U0.